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Venue:
Ballsaal C
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Wednesday
, September 18
09:30 CEST
Introduction to RISC-V - Calista Redmond, RISC-V Foundation
Ballsaal C
09:50 CEST
Rocinante: Motor Control SoC with Integrated RISC-V Core - Dr. Onno Martens, Trinamic Motion Control
Ballsaal C
10:10 CEST
Embedded Software Development for RISC-V Based SoC - Rocco Jonack, Minres Technology GmbH
Ballsaal C
11:00 CEST
SCRx Family of the RISC-V Compatible Processor IP by Syntacore - Alexander Redkin & Pavel Khabarov, Syntacore
Ballsaal C
11:20 CEST
RISC-V SoC FPGA Brings Real-Time to Linux - Jens Huettemann, Microchip Technology
Ballsaal C
11:40 CEST
Machine Learning on Battery Operated Devices at the Very Edge Using a Multi-core RISC-V Based Processor - Martin Croome, GreenWaves
Ballsaal C
13:10 CEST
Fast Start into RISC-V for AIoT with A+ Core - Florian Wohlrab, Andes Technology
Ballsaal C
13:30 CEST
SweRV Core & CHIPS Alliance Initiatives - Ted Marena, Western Digital
Ballsaal C
13:50 CEST
Verifying the Full Scope of RISC-V Integrity - Nicolae Tusinschi, OneSpin
Ballsaal C
14:10 CEST
SiFive Cloud Design Services for IP Evaluation - Kenneth Østby, SiFive
Ballsaal C
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Ballsaal C
Foyer Ballsaal
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Wednesday
, September 18
Venue
Ballsaal C
Foyer Ballsaal
TBA
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