Getting Started with RISC-V Munich

During the presentation, attendees will get an update on the Rocinante development, world’s first motor control SoC with integrated RISC-V core. The working prototype board with toolchain and demo application will be demonstrated to show Rocinante’s capabilities. Moreover, those interested get to see how they can access the motor control technology inside, allowing them to build the next generation of cyber-physical systems.

"MINRES is a global provider for expertise in embedded software development, virtual prototyping and modeling with application specific knowledge in functional safety and interconnect technology. RISC-V ISA standard opens up new possibilities for embedded system development since the open architecture together with extensions offer unparalleled opportunities for energy efficient, low cost embedded systems. But this requires a HW/SW development environment in order to leverage features early in the development. Prototyping and especially the use of Virtual Prototypes is an efficient and effective means to address several challenges in the development of embedded systems.
This session gives an overview and introduction into virtual prototyping, its use, advantages and limitations."

In this talk, we will describe the family of the state-of-the-art RISC-V compatible microprocessor core IP developed by Syntacore with specific focus on details of our 64bit product line and roadmap.

SCRx family now includes eight industry-grade cores with comprehensive features, targeted at different applications: from compact SCR1 MCU core, which is one of the first fully open industry-grade RISC-V compatible cores (introduced in 2017) to the high-performance 64bit Linux-capable multicore SCR7. Different cores can now be used together in heterogeneous multicore clusters with atomics and memory coherency. The SCRx cores deliver competitive performance at low power already in baseline configurations. On the top, Syntacore provides a one-stop workload-specific processor customization service to enable customer designs differentiation via significant performance and efficiency boost. Industry-standard interfacing options support (AHB, AXI4, ACE) enables seamless integration with existing designs. In the session, we detail cores features, benchmarks and collateral availability.

Microchip has unveiled the architecture for a new class of SoC FPGAs that combine the industry's lowest power, mid-range PolarFire® FPGA family with a hardened microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA). Announced at the 2018 RISC-V Summit in Santa Clara, the PolarFire SoC architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. The presentation will discuss this fully customizable, programmable RISC-V platform that allows embedded developers to create innovative Linux-based SoCs tailored for their domain-specific requirements.

Battery operated IoT sensors have, until now, been restricted to simple data sources such as temperature and humidity. But there is increasing interest in processing richer data sources such as images, sounds, and vibrations. These applications require significant processing on the edge device to remain compatible with low power IoT wireless networks such as LoRa, Sigfox, NB-IOT, and BLE. GreenWaves has used the extensibility of the RISC-V ISA and other architectural innovations to produce GAP8, a flexible, programmable IoT Application Processor designed to enable AI in devices at the very edge of the network. The architecture of GAP8 will be reviewed showing how innovation in core design and the use of open hardware can enable companies to address new markets on the internet of things.

RISC-V is changing the processor landscape rapidly. Being open, modular yet compact and innovative RISC-V is THE game-changer. With Fast start into RISC-V, we will not only introduce our free starter, commercial grade core but also show which other options available, ranging from an ultra-low power MCU over a low power medium sized Core up to Linux capable multicore processors based on RISC-V. User-friendly and powerful integrated development environment like AndeSight and associated software and hardware solutions will help RISC-V beginner to accomplish the efficient SoC design. Furthermore, Andes ACE feature further accelerates high performance and enables embedded designers to add customized instructions on their Andes RISC-V CPU cores with ease.

Earlier this year Western Digital released the first production grade, open source RISC-V core, our SweRV Core EH1. Based on community feedback, we have made performance enhancements and upgrades. The SweRV Core along with other open hardware designs and software development tools will be worked on in the CHIPS Alliance organization. CHIPS Alliance will harness the collaboration of organizations and open source developers to create RTL IP, SoCs, complex peripherals and development tools which all it's members will share.

To stand out against the many available options, RISC-V processor core developers must thoroughly verify their designs. This requirement goes beyond Instruction Set Architecture (ISA) compliance checking to include optional ISA features, custom extensions, and microarchitectural implementation choices.

RISC-V system-on-chip (SoC) designers must be able to confirm the integrity of the RISC-V cores they integrate, including proof that no Trojans or hardware vulnerabilities lurk in the design, and verify that the cores are integrated properly into the SoC. Safety-critical applications with strict standards add even more verification requirements.

This talk presents a verification flow covering the full scope of integrity for RISC-V cores and SoCs, spanning functional correctness, safety, security, and trust. It is essential for RISC-V core developers, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources.

Modern SoC design requires scalable solutions for SoC IP and key features. In this talk, SiFive will demonstrate the use of SiFive Core Designer to show how a tuning instruction cache can benefit your workload to optimize performance, area, and efficiency.